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    SubjectRe: SiS 5513 ATA133 support patch for 2.4.19-rc3-ac3
    On Mon, 29 Jul 2002 10:56:26 +0200, Lionel Bouton wrote:

    >On lun, jui 29, 2002 at 09:11:34 +0200, Daniela Engert wrote:
    >> On Mon, 29 Jul 2002 01:37:54 +0200, Lionel Bouton wrote:
    >>
    >>
    >> Lionel,
    >>
    >> as you already figured out, looking at the northbridge IDs is simply
    >> not sufficient to find out which capabilities and register layout the
    >> IDE controller in the southbridge (no matter if integrated or external)
    >> has.
    >>
    >> Some comments:
    >>
    >> 1) the 745 has an integrated southbridge and an ATA/100 capable IDE
    >> controller
    >>
    >
    >I believed so too, but Lei-Chun patch changed it to ATA133.
    >Lei-Chun, could you tell us what we can expect from 745 chips ?

    I have a user report indicating that:

    PCI BIOS V2.10 detected, 2 PCI buses present.
    Found embedded SiS 5513 on 0/2/5
    00: 39 10 13 55 07 00 00 00 D0 80 01 01 00 80 80 00
    10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    20: 01 40 00 00 00 00 00 00 00 00 00 00 19 10 41 0A
    30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    40: 31 81 31 82 31 00 31 00 08 01 E6 33 00 02 00 02
    50: 01 00 01 06 00 00 00 00 00 00 00 00 00 00 00 00
    BusMaster Registers:
    00: 08 00 60 00 58 28 F6 00 00 00 04 00 FC 5F 00 00

    VendorID 1039, DeviceID 5513, Subsystem VendorID 1019, DeviceID 0A41
    IOBase 4000h (Len 10h)

    Host bridge (1039/0745 rev 01) on 0/0/0
    South bridge (1039/0008 rev 00) on 0/2/0

    The primary master is a UDMA 5 disk, and primary slave a UDMA 4 one.

    >> 2) the 646 (and most likely the 645 and others as well) may be paired
    >> with a 961 (ATA/100) or 961B (ATA133) MutIOL southbridge with different
    >> register programming values.
    >>
    >> Thus simply ripping out some northbridge IDs wouldn't prevent
    >> corruption problems.
    >>
    >
    >I don't see why (unless you refer to the 962/963 problem I did mention).
    >If we remove the IDs, the chips will be detected as SiS5513 (ATA_16). If
    >I'm correct, in this mode (only allowing PIO modes and SW/MW DMA modes)
    >all chips are OK.
    >I didn't dig in all specs to check each config register change, but all I
    >saw was OK and I *never* received any data corruption report for a chip that
    >was configured as original SiS5513 (though I have many reports of bad
    >performance due to PIO modes being used in such cases).

    Ok, I think you are right, disabling UDMA mode should be a safe bet.

    Ciao,
    Dani

    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Daniela Engert, systems engineer at MEDAV GmbH
    Gräfenberger Str. 34, 91080 Uttenreuth, Germany
    Phone ++49-9131-583-348, Fax ++49-9131-583-11


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