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SubjectRe: PCI DMA to small buffers on cache-incoherent arch
>>>>> "David" == David S Miller <> writes:

Roland> Or should we leave that usage unless it is observed
Roland> causing problems (since we almost always get lucky and
Roland> don't touch the rest of the cache line near the DMA)?

David> I think passing in a 4 byte chunk and assuming the rest of
David> the cacheline is unmodified is a valid expectation the more
David> I think about it.

Just to make sure I'm reading this correctly, you're saying that as
long as a buffer is OK for DMA, it should be OK to use a
sub-cache-line chunk as a DMA buffer via pci_map_single(), and
accessing the rest of the cache line should be OK at any time before,
during and after the DMA.

David> This means what MIPS is doing is wrong. For partial
David> cacheline bits it can't do the invalidate thing.

If I understand you, this means non-cache-coherent PPC is wrong as
well -- pci_map_single() goes through consistent_sync() and turns

case PCI_DMA_FROMDEVICE: /* invalidate only */
invalidate_dcache_range(start, end);

What alternate implementation are you proposing?

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