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SubjectRe: Memory Barrier Definitions
> forms of processor memory barrier instructions.  It is _very_ expensive
> to blindly force all memory references to be ordered completely to the
> seperate spaces. The use of wmb(), rmb(), and mb() is overloaded in the
> context of PowerPC.

I think I follow

You have

Compiler ordering
CPU v CPU memory ordering
CPU v I/O memory ordering
I/O v I/O memory ordering

and our current heirarchy is a little bit more squashed than that. I'd
agree. We actually hit a corner case of this on the IDT winchip x86 where
we run relaxed store ordering and have to define wmb() as a locked add of
zero to the top of stack - which does have a penalty that isnt needed
for CPU ordering.

How much of this impacts Mips64 ?


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