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SubjectRe: Wrong IRQ distribution on Dual Xeon SMP system (2.4.17).
> Problem:  Wrong interrupts distribution between processors, as a result of
> IO APIC configuration errors
>
> Platform: SuperMicro P4DP6 motherboard (Intel E7500 chipset) with two Intel
> Xeon Processors (512 Kb L2 cache @ 2.2 GHz), 1 Gb PC2100 RAM. Phoenix BIOS
> 1.1a (latest available for this board). Hyper threading enabled, ACPI
> enabled.
>
> Kernel: 2.4.17 Sherman-x330 (MontaVista) - SMP enabled.
>
> Problem Description:
>
> After booting the /proc/interrupts files reads as follows:
>
> CPU0 CPU1 CPU2 CPU3
> 0: 23794 0 0 0 IO-APIC-edge timer
> 1: 1900 0 0 0 IO-APIC-edge keyboard
> 2: 0 0 0 0 XT-PIC cascade
> 4: 0 0 0 0 IO-APIC-edge KGDB-stub
> 9: 0 0 0 0 IO-APIC-edge acpi
> 17: 4718 0 0 0 IO-APIC-level eth0
> NMI: 23672 23672 23672 23672
> LOC: 23649 23648 23648 23646
> ERR: 0
> MIS: 0

P4 based systems don't round-robin interrupts like P3 based systems do.
Check back in the archives, and find one of the interrupt routing patches.
Dave Olien had one, and Ingo Molnar had one, they use slightly different
approaches.

Martin.

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