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SubjectRe: [PATCH] IBM Lanstreamer bugfixes (round 3)
Thus Spake Jeff Garzik:

>I agree to the first part :)
>
>Set cache line size just like drivers/net/acenic.c does, and enable
>memory-write-invalidate...
>

Ok, hopefully below is the section you were referring to:

-------

pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
cls <<= 2;
if (cls != SMP_CACHE_BYTES) {
printk(KERN_INFO " PCI cache line size set incorrectly "
"(%i bytes) by BIOS/FW, ", cls);
if (cls > SMP_CACHE_BYTES)
printk("expecting %i\n", SMP_CACHE_BYTES);
else {
printk("correcting to %i\n", SMP_CACHE_BYTES);
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
SMP_CACHE_BYTES >> 2);
}
}

pci_read_config_word (pdev, PCI_COMMAND, &pcr);

/* Turn off Fast B2B enable */
pcr &= ~PCI_COMMAND_FAST_BACK;
/* Turn on SERR# enable and others */
pcr |= (PCI_COMMAND_SERR | PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY);

pci_write_config_word (pdev, PCI_COMMAND, pcr);
pci_read_config_word (pdev, PCI_COMMAND, &pcr);

------

Out of curiosity, does it in fact make sense to use memory write and
invalidate and set cache line size to 0 in some cases? This seems to go
against the PCI spec, which, if I'm reading it correctly, says that memory
write and invalidate is the same as a memory write, but it guarantees that
at least 1 cache line will be written. So, setting cacheline size =0 would
negate this effect(?)

Kent

>
> Jeff
>
>
>

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