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SubjectRe: 7.52 second kernel compile
Date
Linus Torvalds wrote:

> So on a PII core, you'll see something like
>
> 87.50: 36
> 12.39: 40
>
> ie 87.5% (exactly 7/8) of the TLB misses take 36 cycles, while 12.4%
> (ie 1/8) takes 40 cycles (and I assuem that the extra 4 cycles is due
> to actually loading the thing from the data cache).
>
> Yeah, my program might be buggy, so take the numbers with a pinch of
> salt. But it's interesting to see how on an athlon the numbers are
>
> 3.17: 59
> 34.94: 62
> 4.71: 85
> 54.83: 88
>
> ie roughly 60% take 85-90 cycles, and 40% take ~60 cycles. I don't
> know where that pattern would come from..

You scared me, so I ran the program on my AMD duron. Result are
completely repeatable (4 runs):

4.17: 20
92.89: 21
1.17: 26

4.17: 20
93.00: 21
1.18: 26

4.17: 20
92.86: 21
1.18: 26

4.16: 20
92.78: 21
1.16: 26

Ie, rather violently different from the numbers you quoted for the
Athlon...

$ cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 6
model : 3
model name : AMD Duron(tm) Processor
stepping : 1
cpu MHz : 757.472
cache size : 64 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat
pse36 mmx fxsr syscall mmxext 3dnowext 3dnow
bogomips : 1510.60

Rene.

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