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SubjectRe: 7.52 second kernel compile
On Mon, 18 Mar 2002, Linus Torvalds wrote:

>
> On Mon, 18 Mar 2002, Dieter [iso-8859-15] Nützel wrote:
> >
> > it seems to be that it depends on gcc and flags.
>
> That instability doesn't seem to show up on a PII. Interesting. Looks like
> the athlon may be reordering TLB accesses, while the PII apparently
> doesn't.
>
> Or maybe the program is just flawed, and the interesting 1/8 pattern comes
> from something else altogether.


Umhh, something magic should happen inside the Athlon p/line to explain this :


processor : 0
vendor_id : AuthenticAMD
cpu family : 6
model : 4
model name : AMD Athlon(tm) Processor
stepping : 2
cpu MHz : 999.561
cache size : 256 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov
pat pse36 mmx fxsr syscall mmxext 3dnowext 3dnow
bogomips : 1992.29



$ gcc -o tlb_test tlb_test.c

#APP
rdtsc
#NO_APP
movl %eax, -16(%ebp)
movl -4(%ebp), %eax
addl -12(%ebp), %eax
movl (%eax), %eax
#APP
rdtsc
#NO_APP
movl %eax, -20(%ebp)


98.76: 21



$ gcc -O2 -o tlb_test tlb_test.c

#APP
rdtsc
#NO_APP
movl -16(%ebp), %edx
movl %eax, %ecx
movl (%ebx,%edx), %eax
#APP
rdtsc
#NO_APP
subl %ecx, %eax


97.59: 94


The only thing i can think is that stuff is moved between the two rdtsc
... maybe a barrier should help to have more consistent results.




- Davide


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