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SubjectRe: 7.52 second kernel compile
It would be easy to do with the debug registers on PPC but they're
supervisor level only. Users have no need to profile their code, after
all.

A logic analyzer would be really handy here. Dave, think you can swing
one? :)

I ended up using averages for my tests with the PPC when doing the MM
optimizations. Wall-clock time tells you if you did a good thing or not,
but not what it was that you actually did :)

Any suggestions for a structure, Dave?

} On Mon, 18 Mar 2002, Cort Dougan wrote:
} > The cycle timer in this case is about 16.6MHz.
}
} Oh, you're cycle timer is too slow to be interesting, apparently ;(
}
} We could modify the test program to use more portably timing functions
} and doing the TLB accesses several times over. While this would get
} us something more reasonable on PPC, and be more portable, the results
} would be a bit less accurate because we'd be dealing effectively with
} averages instead of real cycle count samples.
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