Messages in this thread |  | | From | Cort Dougan <> | Date | Mon, 18 Mar 2002 17:27:05 -0700 | Subject | Re: 7.52 second kernel compile |
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It would be easy to do with the debug registers on PPC but they're supervisor level only. Users have no need to profile their code, after all.
A logic analyzer would be really handy here. Dave, think you can swing one? :)
I ended up using averages for my tests with the PPC when doing the MM optimizations. Wall-clock time tells you if you did a good thing or not, but not what it was that you actually did :)
Any suggestions for a structure, Dave?
} On Mon, 18 Mar 2002, Cort Dougan wrote: } > The cycle timer in this case is about 16.6MHz. } } Oh, you're cycle timer is too slow to be interesting, apparently ;( } } We could modify the test program to use more portably timing functions } and doing the TLB accesses several times over. While this would get } us something more reasonable on PPC, and be more portable, the results } would be a bit less accurate because we'd be dealing effectively with } averages instead of real cycle count samples. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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