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SubjectRe: 7.52 second kernel compile
Linus Torvalds writes:

> Btw, here's a program that does a simple histogram of TLB miss cost, and
> shows the interesting pattern on intel I was talking about: every 8th miss
> is most costly, apparently because Intel pre-fetches 8 TLB entries at a
> time.

Here are the results on my 500Mhz G4 laptop:

1.85: 22
17.86: 26
14.41: 28
16.88: 42
34.03: 46
9.61: 48
2.07: 88
1.04: 90

The numbers are fairly repeatable except that the last two tend to
wobble around a little. These are numbers of cycles obtained using
one of the performance monitor counters set to count every cycle.
The average is 40.6 cycles.

This was with a 512kB MMU hash table, which translates to 8192 hash
buckets each holding 8 ptes. The machine has 1MB of L2 cache.

Paul.
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