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    SubjectRe: [Lse-tech] Re: 10.31 second kernel compile

    On Sat, 16 Mar 2002, David Mosberger wrote:
    > ia64 has an optional hardware walker which can operate in "hashed"
    > mode or in "virtually mapped linear page table mode". If you think
    > you can do a TLB lookup faster in software, you can turn the walker
    > off.

    I used to be a sw fill proponent, but I've grown personally convinced that
    while sw fill is good, it needs a few things:

    - large on-chip TLB to avoid excessive trashing (ie preferably thousands
    of entries)

    This implies that the TLB should be split into a L1 and a L2, for all
    the same reasons you split other caches that way (and with the L1
    probably being duplicated among all memory units)

    - ability to fill multiple entries in one go to offset the cost of taking
    the trap.

    Without that kind of support, the flexibility advantages of a sw fill just
    isn't enough to offset the advantage you can get from doing it in
    hardware (mainly the ability to not have to break your pipeline).

    An in-memory hash table can of course be that L2, but I have this strong
    suspicion that a forward-looking chip engineer would just have put the L2
    on the die and made it architecturally invisible (so that moore's law can
    trivially make it bigger in years to come).


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