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    SubjectRe: [Lse-tech] Re: 10.31 second kernel compile
    On Sat, Mar 16, 2002 at 11:58:22AM -0800, Linus Torvalds wrote:
    > This implies that the TLB should be split into a L1 and a L2, for all
    > the same reasons you split other caches that way (and with the L1
    > probably being duplicated among all memory units)

    AMD claims L1, L2 and with hammer an
    I/D split as well. But no TLB load instruction as
    far as I can tell


    --
    ---------------------------------------------------------
    Victor Yodaiken
    Finite State Machine Labs: The RTLinux Company.
    www.fsmlabs.com www.rtlinux.com

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