Messages in this thread | | | Date | Thu, 14 Mar 2002 09:23:22 +0100 | From | Vojtech Pavlik <> | Subject | Re: [patch] PIIX rewrite patch, pre-final |
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On Thu, Mar 14, 2002 at 09:18:08AM +0100, Vojtech Pavlik wrote: > On Thu, Mar 14, 2002 at 08:44:42AM +0100, Daniela Engert wrote: > > > The PIIX3 bug is real, I have several user reports about it! > > Thanks A LOT for the tables, added are some comments from me ... > > > Vendor > > | Device > > | | Revision ATA ATAPI ATA66 ATA133 > > | | | south/host bridge id PIO DMA PIO DMA ATA33 | ATA100| Docs > > | | | | south/host bridge rev. 32bit | 32bit | | | | | avail > > | | | | | | | | | | | | | | > > v v v v v v v v v v v v v v > > > > 0x8086 Intel > > 0x1230 PIIX x x x x - - - - x > > < 02 x - x - - - - - x > > I suppose this means on PIIXes with rev 00 and 01 of the IDE controller > DMA transfers don't work reliably, right? > > > 0x84C4 Orion > > < 04 x - x - - - - - x > > And this means that if there is an 84c4 PCI bridge in the system with > rev less than 04 (04 is OK), then DMA transfers are broken again.
And there is one more Intel chip:
0x1234, the infamous MPIIX. Can do PIO only, 32 bit is OK, has a single channel switchable to primary or secondary, IDETIM is located in registers 6C-6D on the ISA bridge. Docs available.
-- Vojtech Pavlik SuSE Labs - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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