lkml.org 
[lkml]   [2002]   [Feb]   [28]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
Date
SubjectRe: PROBLEM: Timer interrupt lockup on HT machine
Martin Wilck writes:
> Another observation is that on the HT machines (whether or not the
> above problem occurs) almost all interrupts seem to be handled by CPU 0.
>
> CPU 1 gets a few, but in a ratio of about 1:10000 wrt CPU 0.
> CPU 2 and 3 do not see any interrupts at all.
>
> Has anybody heard of these problems yet, and are workarounds available?

I've heard about that IRQ imbalance on MP P4 Xeons from a person at Dell.
My understanding of it is that it's a consequence of the local APIC
priorization changes Intel did in the P4 xAPIC design. (Study Intel's IA32
Vol 3 manual in detail and you'll see them.) Supposedly Ingo Molnar is
working on a solution.

/Mikael
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2005-03-22 13:20    [W:0.041 / U:5.312 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site