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SubjectRe: 2.4.18-rcx: Dual P3 + VIA + APIC
On Sat, 23 Feb 2002 17:22:01 +0000 (GMT)
Alan Cox <alan@lxorguk.ukuu.org.uk> wrote:

> > <4>CPU1<T0:1339376,T1:446448,D:8,S:446460,C:1339380>
> > <4>checking TSC synchronization across CPUs: passed.
> > <4>Waiting on wait_init_idle (map = 0x2)
> > <4>All processors have done init_idle
> >
> > I would say this means the TSC skew fix is broken and shooting down your box. What do you think, Alan?
>
> Seems a reasonable guess. However that TSC skew itself may point to other
> problems. It means one processor started running successfully a little after
> the other. That might be normal behaviour for that board or might point to
> something else

It seems no normal behaviour, I checked several other boards of this type and none had a TSC skew (and all work). Purely guessing I would suggest two try some other 2 processors to verify the behaviour is really processor-independent. Another guess would of course be the MB itself being broken to some extent.

Has anybody ever seen a _working_ skew correction? Is this known-to-work code?

Regards,
Stephan

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