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SubjectRe: readl/writel and memory barriers
> In a quick survey of architectures that need explicit memory barriers to
> enforce ordering of PCI accesses, it seems that alpha and PPC include memory
> barriers inside readl() and writel(), whereas MIPS, sparc64, ia64, and s390

Alpha and PPC include them, x86 its handled by the hardware. __raw_read/write*
are bit more exciting.

> do not include them. (I'm not intimately familiar with these architectures
> so forgive me if I got some wrong...). What is the official story here?

To quote from the Documentation dir..

The read and write functions are defined to be ordered. That is the
compiler is not permitted to reorder the I/O sequence. When the
ordering can be compiler optimised, you can use <function>
__readb</function> and friends to indicate the relaxed ordering. Use
this with care. The <function>rmb</function> provides a read memory
barrier. The <function>wmb</function> provides a write memory barrier.

While the basic functions are defined to be synchronous with respect
to each other and ordered with respect to each other the busses the
devices sit on may themselves have asynchronocity. In paticular many
authors are burned by the fact that PCI bus writes are posted
asynchronously. A driver author must issue a read from the same
device to ensure that writes have occurred in the specific cases the
author cares. This kind of property cannot be hidden from driver
writers in the API.

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