Messages in this thread | | | Date | Mon, 11 Feb 2002 21:32:48 -0800 (PST) | Subject | Re: thread_info implementation | From | "David S. Miller" <> |
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From: Richard Henderson <rth@twiddle.net> Date: Mon, 11 Feb 2002 21:26:44 -0800
On another topic, I'm considering having $8 continue to be current and using the two-insn stack mask to get current_thread_info and measuring the size difference that makes.
I might put 'current' into %g7 on sparc but currently I don't think it's worth it myself.
BTW, your "4 issue" comments assume the cpu can do 4 non-FPU instructions per cycle, most I am aware of cannot and I think ia64 even falls into the "cannot" category. Doesn't it?
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