Messages in this thread | | | Date | Sat, 21 Dec 2002 19:34:10 +0100 (MET) | From | "Maciej W. Rozycki" <> | Subject | Re: PATCH 2.5.x disable BAR when sizing |
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On Fri, 20 Dec 2002, Linus Torvalds wrote:
> > That's exactly the problem on ia64 - it does. > > Could this also be a problem on i386 that we just haven't noticed yet? > > Unlikely. The IO-APIC on x86 is in that region, but it doesn't respond > from external sources, it's not actually on the PCI bus and only visible > from the CPU. And the CPU decodes that address internally and sends it on > the APIC bus and thus PCI devices simply do not matter for it.
That's not true for the I/O APIC. That's only true for the local APIC.
The I/O APIC may be wired to the PCI-ISA bridge, specifically the APICCS# (chip select) line may be driven by that bridge when a PCI cycle targets the area assigned to the I/O APIC. This is certainly the case for discrete implementations, like the i82371SB/AB (PCI-ISA bridge) + i82093AA (I/O APIC) pair, possibly for others, including later I/O APICs integrated into chipsets. Obviously cycles from CPUs travel to the PCI-ISA bridge across the associated PCI bus.
-- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
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