Messages in this thread | | | From | Mikael Pettersson <> | Date | Wed, 30 Oct 2002 21:46:59 +0100 | Subject | Are x86 trap gate handlers safe for preemption? |
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Consider an exception handler like vector 7, device_not_available:
ENTRY(device_not_available) pushl $-1 # mark this as an int SAVE_ALL movl %cr0, %eax testl $0x4, %eax # EM (math emulation bit) jne device_not_available_emulate preempt_stop
Since this is invoked via a trap gate and not an interrupt gate, what's preventing this code from being preempted and resumed on another CPU before the read from %cr0? Another example is the machine_check vector (also trap gate) whose handlers access MSRs.
I'm sure this actually works, but I don't see how.
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