Messages in this thread | | | Subject | Re: [PATCH] IBM Lanstreamer bugfixes | Date | Wed, 30 Jan 2002 20:47:45 +0000 (GMT) | From | Alan Cox <> |
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> effects. I tested by removing all the delays and instead putting > something like: > writew(val, addr); > (void) read(addr); > > instead, to flush the PCI cache. Things seem to be happy. > > Is this the best way to make sure the PCI cache is flushed for writes that > need to happen immediately? I don't see many other drivers doing it...
In many cases its not needed. Devices tend to be structured to avoid having to force pci writes - that by definition is a CPU stall and loses you marks in the benchmarketing and the pretty zdnet graphs.
There other thing it can also hide is pci write merging bugs (which some devices have). For example at least one ethernet chip fails if you do
writew(mac_addr, ioport+foo); writew(mac_addr+2, ioport+foo+2); writew(mac_addr+4, ioport+foo+4);
because the writes get merged and a chip bug causes a bus hang on the 32bit write of the mac address. In that case its not the posting being masked but the merging.
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