Messages in this thread | | | Date | Mon, 21 Jan 2002 16:40:48 +0100 | From | Manfred Spraul <> | Subject | Re: [sched] [patch] migration-fixes-2.5.3-pre2-A1 |
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Ingo Molnar wrote: > > So i think the P6 documentation is a pessimisation of the true situation, > and that we can very well have multiple interrupts on the same priority > level even on older APICs - as long as the local timer interrupt is not > amongst them. > You are right. I tried to reproduce it (force cpu1 to priority 15, send 4 ipis to priority 14 from cpu0, check that all arrive), and it seems that the pIII doesn't drop ipi messages.
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