Messages in this thread | | | Subject | Re: [PATCH] IBM Lanstreamer bugfixes | Date | Fri, 18 Jan 2002 23:19:08 +0000 (GMT) | From | Alan Cox <> |
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> BTW, I don't know what PCI posting effects are...
Ok given
writel(foo, dev->reg); udelay(5); writel(bar, dev->reg);
The pci bridge is at liberty to delay the first write until the second or a read from that device comes along (and wants to do so to merge bursts). It tends to bite people
- When they do a write to clear the IRQ status and don't do a read so they keep handling lots of phantom level triggered interrupts.
- When there is a delay (reset is common) that has to be observed
- At the end of a DMA transfer when people unmap stuff early and the "stop the DMA" command got delayed
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