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SubjectRe: [SOLVED + PATCH]: documented Oops running big-endian reiserfs on parisc architecture
In article <>,
David S. Miller <> wrote:
>Oh thats different! That won't even work %100 correctly on x86. On
>x86 it will "execute", but it won't be atomic.

Actually, it will. Intel definitely discourages it, but they'll lock
both cache-lines if the access is unaligned and crosses. So while they
encourage natural alignment for atomic accesses, I think they also
guarantee that they always work - it ends up being only a performance

I agree that it is bad practice, though, and I bet that the x86 is one
of the very few architectures that _will_ do this naturally.

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