Messages in this thread |  | | Date | Wed, 26 Sep 2001 19:09:11 +0100 | From | Padraig Brady <> | Subject | Re: Locking comment on shrink_caches() |
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Dave Jones wrote:
>On Wed, 26 Sep 2001, Alan Cox wrote: > >>VIA Cyrix CIII (original generation 0.18u) >> >>nothing: 28 cycles >>locked add: 29 cycles >>cpuid: 72 cycles >> > >Interesting. From a newer C3.. > >nothing: 30 cycles >locked add: 31 cycles >cpuid: 79 cycles > >Only slightly worse, but I'd not expected this. >This was from a 866MHz part too, whereas you have a 533 iirc ? > >regards, > >Dave. > Interesting, does the origonal CIII have a TSC? would that affect the timings Alan got?
The following table may be of use to people:
(All these S370) ---------------------------------------------------------------------------------------- core size name code Notes ---------------------------------------------------------------------------------------- samuel 0.18µm Via Cyrix III(C5) (128K L1 0K L2 cache). FPU doesn't run @ full clock speed. samuel II 0.15µm Via C3 (C5B) 667MHz CIII in Dabs are C3's (128K L1, 64K L2 cache), (MMX/3D now!), FPU @ full clock speed. mathew 0.15µm Via C3 (C5B) mobile samuel II with integrated north bridge & 2D/3D graphics. (1.6v) ezra 0.13µm Via C3 (C5C) Debut @ 850MHz rising to 1GHz quickly (1.35v) nehemiah 0.13µm Via C4 (C5X) Debut @ 1.2GHz (128K L1, 256K L2 cache) (SSE) esther 0.10µm Via C4 (C5Y) ?
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C3 availability details: 667 66 / 100 / 133 1.5 Socket 370 L1: 128kB,L2: 64kB 0.15µ 6-12W Mar 2001 733 66 / 100 / 133 1.5 Socket 370 L1: 128kB,L2: 64kB 0.15µ 6-12W May 2001 733 66 / 100 / 133 1.5 Socket 370 L1: 128kB,L2: 64kB 0.15µ 1+ W May 2001 (e series) 750 100 / 133 1.5 Socket 370 L1: 128kB,L2: 64kB 0.15µ 6-12W May 2001 800 100 / 133 1.5 Socket 370 L1: 128kB,L2: 64kB 0.13µ 7-12W May 2001 (ezra)
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