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Subjectparallel port setup code for NSC8739x LPC Super I/O chipsets
Hello,

I've attached a patch for NSC8739x LPC Super I/O chipsets to
enable and configure the parallel port. It would be nice to include this
code to the official linux kernel tree. Thank you.

Jaroslav

-----
Jaroslav Kysela <perex@suse.cz>
SuSE Linux http://www.suse.com
ALSA project http://www.alsa-project.org
--- linux-2.4.10/drivers/parport/parport_pc.c Tue Sep 25 13:01:51 2001
+++ linux/drivers/parport/parport_pc.c Mon Sep 24 10:44:08 2001
@@ -1376,6 +1376,64 @@
}
}

+static void __devinit show_parconfig_nsc39x(int io)
+{
+ int cr30,cr60,cr61,cr70,cr74,crf0,mode4,i=0;
+ char *modes[]={ "Standard (SPP)", /* 0 */
+ "Extended (SPP)",
+ "EPP 1.7",
+ "EPP 1.9",
+ "ECP",
+ "undefined!", /* 5 */
+ "undefined!", /* 6 */
+ "ECP and EPP"};
+
+ /* The registers are called compatible-PnP because the
+ register layout is modelled after ISA-PnP, the access
+ method is just another ... */
+ outb(0x07,io); /* Register 7: Select Logical Device */
+ outb(0x01,io+1); /* LD1 is Parallel Port */
+ outb(0x30,io);
+ cr30=inb(io+1);
+ outb(0x60,io);
+ cr60=inb(io+1);
+ outb(0x61,io);
+ cr61=inb(io+1);
+ outb(0x70,io);
+ cr70=inb(io+1);
+ outb(0x74,io);
+ cr74=inb(io+1);
+ outb(0xf0,io);
+ crf0=inb(io+1);
+ mode4=(cr30 & 0x01) ? inb((cr60<<8)|cr61) : 0;
+
+ printk("NSC8739x LPT Config: cr_30=%02x 60,61=%02x%02x "
+ "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0);
+ printk("NSC8739x LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
+ (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f );
+ if ((cr74 & 0x07) > 3)
+ printk("dma=none\n");
+ else
+ printk("dma=%d\n",cr74 & 0x07);
+ printk("NSC8739x LPT Config: Port mode=%s%s\n", modes[crf0 >> 5],
+ (crf0 & 0xe0) == 0xe0 ? ((mode4 & 0x10) ? " 1.9" : " 1.7") : "");
+ printk("NSC8739x LPT Config: Extended registers at 0x%x are%s accessible\n",
+ ((cr60<<8)|cr61) + 0x400, (crf0 & 0x10) ? "" : " not");
+
+ if(cr30 & 0x01) { /* the settings can be interrogated later ... */
+ while((superios[i].io!= 0) && (i<NR_SUPERIOS))
+ i++;
+ if(i==NR_SUPERIOS)
+ printk("Super-IO: too many chips!\n");
+ else {
+ superios[i].io = (cr60<<8)|cr61;
+ superios[i].irq = cr70&0x0f;
+ superios[i].dma = (((cr74 & 0x07) > 3) ?
+ PARPORT_DMA_NONE : (cr74 & 0x07));
+ }
+ }
+}
+
static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid)
{
char *type=NULL;
@@ -1537,6 +1595,16 @@
decode_smsc(io,key,oldid,oldrev);
}

+static void __devinit nsc39x_check(int io)
+{
+ if (inb(io) == 0xff)
+ return;
+ outb(0x20,io);
+ if (inb(io+1) != 0xea)
+ return;
+ show_parconfig_nsc39x(io);
+}
+

static void __devinit detect_and_report_winbond (void)
{
@@ -1559,6 +1627,13 @@
smsc_check(0x3f0,0x44);
smsc_check(0x370,0x44);
}
+
+static void __devinit detect_and_report_nsc (void)
+{
+ printk("NSC Super-IO detection, now testing Ports 2E, 4E ...\n");
+ nsc39x_check(0x2E);
+ nsc39x_check(0x4E);
+}
#endif /* CONFIG_PARPORT_PC_SUPERIO */

static int __devinit get_superio_dma (struct parport *p)
@@ -2809,6 +2884,7 @@
#ifdef CONFIG_PARPORT_PC_SUPERIO
detect_and_report_winbond ();
detect_and_report_smsc ();
+ detect_and_report_nsc ();
#endif

/* Onboard SuperIO chipsets that show themselves on the PCI bus. */
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