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> That seems amazingly dumb. You'd think a new processor design would
> optimize parallel computation over calls, but what do I know?

They try to. Take a look at the trace cache on the Pentium IV. They certainly
seem to have badly screwed the chip design up elsewhere but the trace cache
has some very clever ideas in it

> were so damn obstinate about "every instruction fits in 32 bits"
> and refused to have "call 32 bit immediate given in next word" not
> to mention a "load 32bit immediate given in next word".
> Note, the superior x86 instruction set has a 5 byte call immediate.

Some do. After all there is nothing unrisc about

call [ip]++

Maybe the idea died with the PDP-11 designers 8)


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