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On Sun, Jul 08, 2001 at 08:08:24PM -0400, Pete Zaitcev wrote:
> Register windows do help some, in that sense ia64 is a big
> step forward ofver x86.

It seems to me that x86 instruction set has lived long enough to
become efficient again. Register windows I think are bad. I'd rather
see a couple of hundred K of 1 cycle memory that the compiler/programmer
could use. But then I don't like the property "test for 1 year
and still don't uncover the production case where there is a window
spill that comes at just the wrong time when the write cache is
full, ... - and timing changes by hundreds of microseconds."

>As I read what Linus wrote, he talked
> about a different thing: inside a procedure you do not
> know whence you are called, therefore you must start scheduling
> anew from the first instruction of the procedure; before your

This is a hard part for any vliw type machine - if the compiler
can't figure it out or if the processor requires a sync point, then
performance will be terrible. My understanding is that this is
just a merced problem, not a ia64 fundamental, but it seems hard.
As Alan points out, the PIV tries to do better with a trace cache
so
code;call x; code
is essentially, dynamically inlined by caching
code;code of x; code
if I understand it right and that's pretty cool
- maybe mckinley will use the same technique if
the compiler can't figure it out.


Anyway, any processor that does badly on calls is going to be
a disaster, the real question is when it's good to use assembler
escapes.

> You must take into account that early riscs had miniscule dies,
> for example the first Fujitsu made SPARC had 10,000 gates
> all told. An alignment to the next instruction wastes hardware,
> and, perhaps, a clock cycle.

PowerPC has no excuse.

>
> -- Pete
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