[lkml]   [2001]   [Jun]   [5]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRe: Missing cache flush.

    On Tue, 5 Jun 2001, David Woodhouse wrote:

    > said:
    > > Chris Wedgwood writes:
    > > > What if the memory is erased underneath the CPU being aware of
    > > > this? In such a way ig generates to bus traffic...
    > > This doesn't happen on x86. The processor snoops all transactions
    > > done by other agents to/from main memory. The processor caches are
    > > always up to date.
    > No. My original mail presented two situations in which this assumption is
    > false.
    > 1. Bank-switched RAM. You want to force a writeback before switching pages.
    > I _guarantee_ you that the CPU isn't snooping my access to the I/O port
    > which sets the latch that drives the upper few address bits of the RAM
    > chips.
    > 2. Flash. A few writes of magic data to magic addresses and a whole erase
    > block suddenly contains 0xFF. The CPU doesn't notice that either.

    3. Buggy implementations like the Cyrix 486es that don't properly maintain
    cache coherency.


    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to
    More majordomo info at
    Please read the FAQ at

     \ /
      Last update: 2005-03-22 12:54    [W:0.021 / U:2.312 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site