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    SubjectRe: Missing cache flush.


    On Tue, 5 Jun 2001, David Woodhouse wrote:

    >
    > davem@redhat.com said:
    > > Chris Wedgwood writes:
    > > > What if the memory is erased underneath the CPU being aware of
    > > > this? In such a way ig generates to bus traffic...
    >
    > > This doesn't happen on x86. The processor snoops all transactions
    > > done by other agents to/from main memory. The processor caches are
    > > always up to date.
    >
    > No. My original mail presented two situations in which this assumption is
    > false.
    >
    > 1. Bank-switched RAM. You want to force a writeback before switching pages.
    > I _guarantee_ you that the CPU isn't snooping my access to the I/O port
    > which sets the latch that drives the upper few address bits of the RAM
    > chips.
    >
    > 2. Flash. A few writes of magic data to magic addresses and a whole erase
    > block suddenly contains 0xFF. The CPU doesn't notice that either.

    3. Buggy implementations like the Cyrix 486es that don't properly maintain
    cache coherency.

    kira.

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