Messages in this thread |  | | Date | Fri, 4 May 2001 10:44:00 -0700 (PDT) | From | Linus Torvalds <> | Subject | Re: Possible PCI subsystem bug in 2.4 |
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On 4 May 2001, Eric W. Biederman wrote: > > There are a couple of options here. > 1) read the MTRRs unless the BIOS is braindead it will set up that area as > write-back. At any rate we shouldn't ever try to allocate a pci region > that is write-back cached.
This one I'd really hesitate to use. We do _not_ want to trust the BIOS any more than necessary (obviously trusting even the e820 was too much), and especially wrt MTRR's we know that there are too many buggy bioses already out there.
> 2) read the memory locations from the northbridge. It's not possible > on every chipset (lack of documentation) but with the linuxBIOS > project we code for a couple of them, and we are working on more > all of the time.
This will be easy.
In fact, we can easily "mix" different heuristics. Ie we'd do the simple thing I suggested in setup_arch(), and use that as a "base guess", and then we can have incremental improvements on that guess that might be chipset-specific or might depend on other information that is not necessarily generic (things like existing PCI programming etc).
Linus
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