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SubjectRe: alpha iommu fixes

Alan Cox writes:
> Ok how about a PIV Xeon with 64Gb of memory and 5 AMI Megaraids, which are
> limited to the low 2Gb range for pci mapping and otherwise need bounce buffers.
> Or how about any consistent alloc on certain HP machines which totally lack
> coherency - also I suspect the R10K on an O2 might fall into that - Ralf ?

If they need bounce buffers because of a device specific DMA range
limitation (this is what I gather this is), then the PCI dma interface
is of no help to this case.

> Look at the history of kernel API's over time. Everything that can
> go wrong eventually does.

I agree, and it will be dealt with in 2.5.x

The scsi layer in 2.4.x is simply not able to handle failure in these
code paths, as Gerard Roudier has mentioned.

Later,
David S. Miller
davem@redhat.com
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