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SubjectRe: Possible PCI subsystem bug in 2.4
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"Maciej W. Rozycki" <macro@ds2.pg.gda.pl> writes:

> On 4 May 2001, Eric W. Biederman wrote:
>
> > The example that sticks out in my head is we rely on the MP table to
> > tell us if the local apic is in pic_mode or in virtual wire mode.
> > When all we really have to do is ask it.
>
> You can't. IMCR is write-only and may involve chipset-specific
> side-effects. Then even if IMCR exists, a system's firmware might have
> chosen the virtual wire mode for whatever reason (e.g. broken hardware).

Admittedly you can't detect directly detect IMCR state. But
triggering an interrupt on the bootstrap processor local apic, and
failing to receive it should be proof the IMCR is at work.
Alternatively if I'm wrong about the wiring disabling all interrupts
at the apic level and receiving one is a second proof that IMCR is at
work. Further I don't think a processor with an onboard apic, works
with an IMCR register.

What I was thinking of earlier is that you can detect an apic or
ioapic in virtual wire mode, which the current code and the intel MP
spec treats as the opposite possibility.

Eric



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