Messages in this thread | | | Date | Wed, 28 Mar 2001 17:39:29 -0500 | From | Dennis <> | Subject | Re: New gigabit cards |
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At 04:20 PM 03/28/2001, Jeff Garzik wrote: >Scott Laird wrote: > > According to the drivers, the 1000TPC uses the NS DP83820. According to > > the DP83820's datasheet, it has a 8k Tx buffer and a 32k Rx buffer. > > That's a bit shy of the 512k-1M that older cards use :-(. At wire speed, > > that means that you'll have to service the NIC's interrupt within ~60 us > > on transmit and ~250 us on receive. That seems rather optimistic. > >Are you assuming one interrupt per packet? > >GigE drivers employ interrupt mitigation, large rings, and sometimes >resort to polling instead of servicing interrupts, and other >techniques. Tiny buffers are ugly, but you can deal with them...
No, thats wrong. Its not about servicing the interrupt, its about access to the bus.
The cards are busmasters, so the rings and data get pushed into memory directly from the controller. A 32-bit PCI bus is only a 1GB bus...but not really because you cant burst continuously so you can never achieve sustained throughtput of 1Gb.. The data must be output to system ram, but the card must "get" the bus before it can transfer, and there are other devices on the bus. The "buffer" is to handle the backup, ie the time that the card cant transfer data to ram because it doesnt have the bus because another card or your ide controller has it. The larger the buffer, the longer the hold-off period before you have to abort frames. If you fill the buffer, you have to dump the frame and clear the buffer for the next one because there is nowhere to store the bits. On a 64 bit, 66mhz bus (its 8 times faster than 32bit), you can burst data out and you only need the bus 1/8th of the time. On a 32bit bus, you need more buffer space because you need the bus all the time to keep up with the data, which is not actually possible.
Ring failures are local issues (ie you must service data faster than it comes in), but thats not hard with todays processors. but having large rings will not alleviate bus failures.
As an example, you can do T1 on a PCI bus with almost no buffer (maybe 64 bytes) because the bus is so much faster then the transfer rate that there is very little chance of falling behind. At 1Gb its much different.
Dennis
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