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    SubjectRe: The IO problem on multiple PCI busses
    >Many platforms, sparc64 included, do not have an ISA IO space nor do
    >they provide VGA accesses at all.
    >If things such as XFree86 are coded for such platforms to not require
    >VGA accesses (the 'ati' driver is already like this when certain
    >build time defines are set), this could become a non-issue in this

    What I call ISA IOs here doesn't necessarily mean there's an ISA bridge
    on the PCI. In fact, VGA cards usually don't live behind such a bridge
    while still requiring occasionally access to the "legacy" ISA IO addresses.

    On PPC, we don't have an "IO" space neither, all we have is a range of
    memory addresses that will cause IO cycles to happen on the PCI bus. But
    we can have one per bus, thus causing this need for several "legacy" IO
    spaces (each bus can have IO addresses in the range 0-64k).

    The typical problem that happens right now is a VGA card in the AGP slot
    and a VGA card in a PCI slot. Both may (depending on the card) need
    access to the legacy VGA IO addresses on the PCI bus on which they are
    located. So in this case, we clearly have 2 legacy busses, av ailable at
    2 different physical memory addresses in the CPU space. What we can do is
    use mapping tricks to map the contiguously in kernel virtual space so
    that only an "offset" allows to go from tone to the other with inb/outb.
    Without that, we need to create new versions of inb/outb that take a bus


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