Messages in this thread |  | | Date | Fri, 9 Feb 2001 13:06:53 +0100 (MET) | From | "Maciej W. Rozycki" <> | Subject | Re: [PATCH] Re: UP APIC reenabling vs. cpu type detection o |
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On Fri, 9 Feb 2001, Mikael Pettersson wrote:
> (I had a theory about inspecting the APIC_LVTPC "Delivery Status" > field, but unfortunately it doesn't seem to get set if a counter > overflowed while LVTPC was masked. Perhaps it's because NMIs are > edge-triggered.)
The delivery status bit gets only set if an interrupt got accepted (that implies it was unmasked at the moment) but its delivery is held pending due to some reason. It may happen when the target CPU has its interrupts masked or the target local APIC cannot accept it due to a higher task priority or no free slots. The semantics of the bit is the same for both local and I/O APIC interrupts.
-- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
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