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SubjectRe: [PATCH] Re: UP APIC reenabling vs. cpu type detection o
On  9 Feb 01 at 13:10, Maciej W. Rozycki wrote:
> On Fri, 9 Feb 2001, Petr Vandrovec wrote:
>
> > Unfortunately both these ways needs intimate knowledge of how UP NMI
> > watchdog works in each kernel, and it is incompatible with other
> > perfctr uses. Probably I'll switch perfctr delivery to some real
> > maskable interrupt while VMware VM owns CPU - if it is possible.
> > Then interrupt should be still pending after VM does __sti().
>
> Why do you need to mask NMI at all?

Because of you must provide some function which handles NMI, and as
you cannot switch IDT and CR3 atomically together, NMI handler has
to be on same address in both address spaces - at least temporary.
And in addition NMI handler in VM would have to switch address spaces
back, execute NMI handler, and return CPU/MMU back to previous state -
which may be just in the middle of normal VM<->Linux transition, so
this context switching cannot use any global variable, it must
save complete CPU/MMU state on stack. And it must not use any spinlock.

If you have any idea how it can be done with NMI unmasked all the way
around...
Thanks,
Petr Vandrovec
vandrove@vc.cvut.cz

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