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SubjectRe: [PATCH] Re: UP APIC reenabling vs. cpu type detection o
On Thu, 8 Feb 2001, Petr Vandrovec wrote:

> So it came to my mind - why (on K7 we easy can, as counter has 48 bits)
> we do not reload NMI watchdog in each timer interrupt with 5sec timeout,
> and if we receive even one NMI, we are locked up? It should increase
> performance, as we'll do same number of MSR writes anyway (100/s), but
> we will not receive any NMI during normal operation, so we save time
> spent in processing this. Or do I miss something?

I guess it's the external watchdog heritage. The code is common for both
kinds of the watchdog at the moment. It might get separated, I suppose.

+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+ e-mail:, PGP key available +

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