Messages in this thread |  | | Date | Fri, 2 Feb 2001 19:12:52 +0100 (CET) | From | Gérard Roudier <> | Subject | Re: [patch] 2.4.0, 2.4.0-ac12: APIC lock-ups |
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On Fri, 2 Feb 2001, Maciej W. Rozycki wrote:
> On Thu, 1 Feb 2001, Andrew Morton wrote:
> +/* > + * It appears there is an erratum which affects at least the 82093AA > + * I/O APIC. If a level-triggered interrupt input is being masked in > + * the redirection entry while the interrupt is send pending (its > + * delivery status bit is set), the interrupt is erroneously > + * delivered as edge-triggered but the IRR bit gets set nevertheless. > + * As a result the I/O unit expects an EOI message but it will never > + * arrive and further interrupts are blocked for the source. > + * > + * A workaround is to set the trigger mode to edge when masking > + * a level-triggered interrupt and to revert the mode when unmasking. > + * The idea is from Manfred Spraul. --macro > + */
Is the below idea feasible or just stupid:
Once a level-sensitive interrupt has been accepted by a local APIC, the IO APIC will wait for the EIO message prior to delivering again this interrupt. Therefore masking a level-sensitive interrupt once it has been delivered and prior to EIOing it should not race with the APIC hardware.
So, why not using a pure software flag in memory and only tampering the things if the offending interrupt is actually delivered ? If the given interrupt is delivered and the software mask is set we could simply do:
- MASK the given interrupt - EOI it. - return
Gérard.
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