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SubjectRe: mpparse.c question
On Fri, 2 Feb 2001, Manfred wrote:

> What's the purpose of of the irq_2_pin in io_apic.c?

Just for what the comment says: to map our IRQ number to an apic:pin
entity in O(1). It has to be fast! You would have to parse the MP table
otherwise -- see pin_2_irq().

> I assume that I overlook something, but afaics the code allows one
> physical interrupt source (e.g. INTA from device 9 on pci bus 0) to
> arrive at multiple ioapic pins.

That's secondary, AFAIK.

> Can that happen, is that important?
>
> Silly question: Why can't we ignore all but the first pin? If we don't
> enable the additional pins, we don't have to disable them during
> disable_irq().

Possibly yes -- I haven't seen such a system.

> disable_irq() and enable_irq() seem to be the only users of irq_2_pin.

That's why it has to be fast.

> Btw, is is correct that the isa irq's are always connected to the first
> io apic? find_isa_irq_pin() doesn't handle that, and the caller just
> access io apic 0.

It appears it happens so for all systems checked so far. The MPS does
not seem to enforce this configuration, so we might relax this dependency
for flexibility. Note that not only find_isa_irq_pin() hardcodes this
assumption -- setup_ExtINT_IRQ0_pin() does as well, for example.

Maciej

--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +

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