Jamie Lokier wrote:
> 
> > > Ben, fancy writing a boot-time test?
> > >
> > I'd never rely on such a test - what if the cpu checks in 99% of the
> > cases, but doesn't handle some cases ('rep movd, everything unaligned,
> > ...'.
> 
> A good point.  The test results are inconclusive.
> 
> > And check the Pentium III erratas. There is one with the tlb
> > that's only triggered if 4 instruction lie in a certain window and all
> > access memory in the same way of the tlb (EFLAGS incorrect if 'andl
> > mask,<memory_addr>' causes page fault)).
> 
> Nasty, but I don't see what an obscure and impossible to work around
> processor bug has to do with this thread.  It doesn't actually change
> page fault handling, does it?
>
Page fault handling is unchanged, but perhaps there are other races. And
note that these races wouldn't be processor bugs - the spec nowhere
guarantee the behaviour you assume.

Ben tries to prove that the current cpu _never_ sets the dirty bit
without checking the present bit.

A very simple test might be

cpu 1:
	cli();
	a = 0; b = 0; m = 0;
	flush_local_tlb_page(a);
	flush_local_tlb_page(b);
	flush_local_tlb_page(a);
	while(!m);
	while (!a && !b);
	a = 1;

cpu 2:
	<wait>
	cli();
	both ptes for a and b as writable, not dirty.
	m = 1;
	udelay(100);
	change the pte of a to not present.
	wmb();
	b = 1;

Now start with variants:
change to read only instead of not present
a and b in the same way of the tlb, in a different way.
change pte with write, change with lock;
.
.
.

But you'll never prove that you tested every combination.

--
	Manfred
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