Messages in this thread | | | Date | Thu, 15 Feb 2001 20:19:45 +0100 | From | Jamie Lokier <> | Subject | Re: x86 ptep_get_and_clear question |
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Kanoj Sarcar wrote: > > Is the sequence > > << lock; > > read pte > > pte |= dirty > > write pte > > >> end lock; > > or > > << lock; > > read pte > > if (!present(pte)) > > do_page_fault(); > > pte |= dirty > > write pte. > > >> end lock; > > No, it is a little more complicated. You also have to include in the > tlb state into this algorithm. Since that is what we are talking about. > Specifically, what does the processor do when it has a tlb entry allowing > RW, the processor has only done reads using the translation, and the > in-memory pte is clear?
Yes (no to the no): Manfred's pseudo-code is exactly the question you're asking. Because when the TLB entry is non-dirty and you do a write, we _know_ the processor will do a locked memory cycle to update the dirty bit. A locked memory cycle implies read-modify-write, not "write TLB entry + dirty" (which would be a plain write) or anything like that.
Given you know it's a locked cycle, the only sensible design from Intel is going to be one of Manfred's scenarios.
An interesting thought experiment though is this:
<< lock; read pte pte |= dirty write pte >> end lock; if (!present(pte)) do_page_fault();
It would have a mighty odd effect wouldn't it?
-- Jamie - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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