Messages in this thread |  | | Date | Fri, 7 Dec 2001 13:25:05 +0100 | From | Kurt Garloff <> | Subject | Re: IDE DMA on AXP & barriers |
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On Thu, Dec 06, 2001 at 12:59:35PM +0300, Ivan Kokshaysky wrote: > On Thu, Dec 06, 2001 at 06:13:15AM +0100, Kurt Garloff wrote: > > I would imagine that the following barriers are nacessary: > > * After setting up the IDE DMA tables (PRD) and having the data there, > > we need to have a barrier before telling the controller to do DMA. > > Actually, we have more than one - the memory barriers are hidden in outX() > macros.
You seem to be right. Here are the results of my investigation: * IDE DMA on reads just works fine * IDE DMA on writes does produce corruption of a couple of bytes at offsets of multiples of PAGE_SIZE (8k) * If I limit the DMA SG segments to not cross the page boundaries, DMA write seems to work. (I see occasional DMA timeouts though, so it might be necessary to limit the SG table length, or maybe to disable all the debugging printks currently active.)
Expect a patch soon.
The sg tables are set up correctly, AFAICS. The only thing which makes me wonder, is why the EOT bit is not set on the last table entry. But it does not seem to make a difference for the CMD646.
So I wonder where the bug actually is. Somewhere in hardware; but I wonder whether the CMD646 or the 2117x (PYXIS/CIA) is to blame. The QLogicISP seems to happily do BM-DMA, so I'd point to the CMD646. OTOH, the QLogic sits on the 2nd PCI bus (32bit), which could make a difference as well.
Regards, -- Kurt Garloff <garloff@suse.de> Eindhoven, NL GPG key: See mail header, key servers Linux kernel development SuSE GmbH, Nuernberg, DE SCSI, Security [unhandled content-type:application/pgp-signature] |  |