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SubjectRe: Athlon /proc/cpuinfo anomaly [minor]

The results of "dmesg" on my dual-Athlon show a (rather comical)
discrepancy, it's not a big deal - just funny (to me)....

I was just wondering if this was a similar behavior to the earlier posts on
this topic:


Intel MultiProcessor Specification v1.4
Virtual Wire compatibility mode.
OEM ID: TYAN Product ID: GUINNESS APIC at: 0xFEE00000
Processor #1 Pentium(tm) Pro APIC version 16
Processor #0 Pentium(tm) Pro APIC version 16
I/O APIC #2 Version 17 at 0xFEC00000.
Processors: 2


Intel machine check reporting enabled on CPU#0.
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 256K (64 bytes/line)
CPU: After vendor init, caps: 0183fbff c1c7fbff 00000000 00000000
CPU: After generic, caps: 0183fbff c1c7fbff 00000000 00000000
CPU: Common caps: 0183fbff c1c7fbff 00000000 00000000
CPU0: AMD Athlon(tm) Processor stepping 04
per-CPU timeslice cutoff: 731.77 usecs.


Intel machine check reporting enabled on CPU#1.
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 256K (64 bytes/line)
CPU: After vendor init, caps: 0183fbff c1c7fbff 00000000 00000000
CPU: After generic, caps: 0183fbff c1c7fbff 00000000 00000000
CPU: Common caps: 0183fbff c1c7fbff 00000000 00000000
CPU1: AMD Athlon(tm) Processor stepping 04
Total of 2 processors activated (5564.00 BogoMIPS).


- Matt



At 01:19 PM 11/21/2001 +0100, Dave Jones wrote:
>On Wed, 21 Nov 2001, Jens Axboe wrote:
>
> > Strange, I was pretty sure that earlier 2.4.x got it right. Oh well.
>
>*shrug* As we don't do any setting of this string, all I can guess
>at is that the new seqfile based /proc/cpuinfo code is stricter
>about getting the info from the right CPU than the older code was.
>
>Though I'm not sure why, as the older code just read from the
>per-CPU structs anyway. Most odd.
>
>regards,
>Dave.
>
>--
>| Dave Jones. http://www.codemonkey.org.uk
>| SuSE Labs
>
>-
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Matthew Sell
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