Messages in this thread |  | | From | "Paul Fulghum" <> | Subject | Re: PCI Device Setup Question | Date | Fri, 5 Oct 2001 08:49:53 -0500 |
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Joachim Martillo wrote:
> These cards use the PLX9050 PCI interface chip ... > The cards are never masters and do no support > PCI PREFETCH and if PCI transactions are made > to them that relate to PCI PREFETCH, they become > confused and hang. ... > The PCI bus driver allocates the sab8253x registers > as prefetchable memory resources.
The PCI9050 LAS0RR local configuration register controls whether the address range is marked prefetchable or not. If bit 3 is set, then the range is marked as prefetchable in Bit 3 of PCI configuration register BAR2.
I would verify that the EEPROM attached to the PCI9050 is setup to program the LAS0RR bit 3 to zero to mark the address range as *not* supporting prefetch.
Paul Fulghum, paulkf@microgate.com Microgate Corporation, www.microgate.com
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