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SubjectRe: please revert bogus patch to vmscan.c
Actually, they swung the pendelum the other way for the 64-bit chips.  The
VSID's (MM contexts) are indirectly accessed via a hash-table (with an on
chip TLB-style cache called a SLB).

The speedup from using the software table-walk actually came from emulating
x86 instead of using the native hash tables. Pretty slick that emulating a
30-year old MMU and improves performance on the PowerPC, eh?

There was an April Fools Microprocessor reports describing a processor that
had gone 64-bit and had a "twisted gothic nightmare of twisted logic" based
MMU that involved XOR-ing addresses with random numbers. They were
unwittingly predicting the future of the PPC MMU.

The nightmares and shakes have never ended for me, either. Sorry about
that, man.

} Gods, I hope they have reconsidered that in their 64-bit chips. The 32-bit
} hash chains may be ugly, but the architected 32/64-bit MMU stuff is just
} so incredibly baroque that it makes any other MMU look positively
} beautiful ("Segments? Segments shmegments. Big deal").
}
} I still have the occasional nightmares about the IBM block diagrams
} "explaining" the PowerPC MMU in their technical documentation.
}
} There's probably a perfectly valid explanation for them, though (*).
}
} Linus
}
} (*) Probably along the lines of the designers being so high on LSD that
} they thought it was a really cool idea. That would certainly explain it in
} a very logical fashion.
}
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