Messages in this thread |  | | Date | Sat, 13 Oct 2001 16:17:14 +0200 (MET DST) | From | Mikael Pettersson <> | Subject | Re: [PATCH] Pentium IV cacheline size. |
| |
On Sat, 13 Oct 2001 12:57:33 +0100, Dave Jones wrote: >Currently, we're using a L1_CACHE_SHIFT value of 7 >for Pentium 4, which equates to 128 byte cache lines. >Curious, I dumped the info on the only P4 I could find, >and noticed they were 64 byte. >Upon checking the documentation, they're 64 byte there too. >Is this just a thinko on someones part, or was there a >rationale behind this that I've not realised ?
According to the P4 and Xeon optimisation manual (#248966-03), the L1 cache has a 64-byte line size and the L2 cache has a 128-byte line size. (Page 1-18, Table 1-1.) Perhaps someone just confused the two, or the distinction wasn't known when the initial P4 support was added to the kernel.
/Mikael - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
|  |