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SubjectRe: [PATCH] Pentium IV cacheline size.

On Sat, 13 Oct 2001, Dave Jones wrote:
> Currently, we're using a L1_CACHE_SHIFT value of 7
> for Pentium 4, which equates to 128 byte cache lines.

Well, the fact is, that from a SMP standpoint, the 128 bytes is the
correct one: the L2 is 128 bytes wide.


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