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SubjectRe: [Lse-tech] Re: RFC: patch to allow lock-free traversal of lists with
Albert D. Cahalan writes:

> This looks an awful lot like the PowerPC architecture.
> In an SMP system, one would most likely mark pages as
> requiring coherency. This means that stores to a memory
> location from multiple processors will give sane results.
> Ordering is undefined when multiple memory locations are
> involved.

The current PowerPC Architecture spec actually has a paragraph that
says that where a processor does two loads and the second load depends
on the first (i.e. the result from the first load is used in computing
the address for the second load), that they have to be performed in
program order with respect to other processors. In other cases you do
need a barrier as you say.

This constraint has evidently been added since the original PPC
architecture book was published. I strongly doubt that any of the
older PPC implementations would violate that constraint though.

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