lkml.org 
[lkml]   [2001]   [Oct]   [12]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: P4 SMP load balancing

Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

> > ovendev:~# cat /proc/interrupts
> > CPU0 CPU1
> > 0: 6348212 0 IO-APIC-edge timer
> > 1: 2 0 IO-APIC-edge keyboard
> > 2: 0 0 XT-PIC cascade
> > 8: 1 0 IO-APIC-edge rtc
> > 9: 0 0 IO-APIC-edge acpi
> > 16: 92620 0 IO-APIC-level eth0
> > 18: 5085 0 IO-APIC-level aic7xxx, aic7xxx
> > NMI: 0 0
> > LOC: 6348388 6348427
> > ERR: 0
> > MIS: 0
>
> I don't think this should happen. In the event of both procs having equal
> priority (linux never changes them, so they always do), we should fall back
> to the arbitration priority of the lapic. Whether you have 1 or 2 I/O apics
> working shouldn't make a difference.

The P 4 has a new apic, and lowest priority delivery doesn't work
anymore.

<<<<<<< Chapter 7.6.10 of 24547202.pdf
In operating systems that use the lowest priority interrupt delivery
mode
but do not update the TPR, the TPR information saved in the chipset will
potentially cause the interrupt to be always delivered to the same
processor from the logical set. This behavior is functionally backward
compatible with the P6 family processor but may result in unexpected
performance implications.
<<<<<<< (search for 245472 on google for the pdf file)


--
Manfred
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2005-03-22 13:08    [W:0.038 / U:1.232 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site