lkml.org 
[lkml]   [2001]   [Jan]   [24]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: ioremap_nocache problem?
From
Date
Timur Tabi <ttabi@interactivesi.com> writes:
> ** Reply to message from David Wragg <dpw@doc.ic.ac.uk> on 24 Jan 2001
> 00:50:20 +0000
> > (x86 processors with PAT and IA64 can set write-combining through
> >page flags. x86 processors with MTRRs but not PAT would need a more
> >elaborate implementation for write-combining.)
>
> What is PAT? I desperately need to figure out how to turn on write
> combining on a per-page level. I thought I had to use MTRRs, but now
> you're saying I can use this "PAT" thing instead. Please explain!

PAT is basically the MTRR memory types on a per-page basis. It adds a
new flag bit to the x86 page table entry, then that bit together with
the PCD and PWT bits is used to do a look-up in an 8-entry table that
gives the effective memory type (the table is set through an MSR).
All the details are in the Intel x86 manual, volume 3
<URL:http://developer.intel.com/design/pentium4/manuals/> (at the end
of chapter 9).

Quite a lot of the x86 CPUs out there support PAT: The PII except the
first couple of models, the Celeron except the first model, the PIII,
all PII and PIII Xeons, the P4, all AMD K7 models. I'm guessing, but
I suspect that the majority of x86 CPUs supporting write combining in
any form that have been made also support PAT.

I wish Intel had put PAT in the PPro, rather than messing everyone
around with MTRRs (MTRRs are good for BIOS writers, but a pain for
everyone else).


David Wragg
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2005-03-22 13:22    [from the cache]
©2003-2011 Jasper Spaans