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SubjectRe: Inefficient PCI DMA usage (was: [experimental patch] UHCI updates)
Date
Johannes Erdfelt writes:
> On Fri, Jan 19, 2001, Miles Lane <miles@megapathdsl.net> wrote:
> > Johannes Erdfelt wrote:
> >
> > > TODO
> > > ----
> > > - The PCI DMA architecture is horribly inefficient on x86 and ia64. The
> > > result is a page is allocated for each TD. This is evil. Perhaps a slab
> > > cache internally? Or modify the generic slab cache to handle PCI DMA
> > > pages instead?
> >
> > This might be the kind of thing to run past Linus when the 2.5 tree
> > opens up. Are these inefficiencies necessary evils due to workarounds
> > for whacky bugs in BIOSen or PCI chipsets or are they due to poor
> > design/implementation?
>
> Looks like poor design/implementation. Or perhaps it was designed for
> another reason than I want to use it for.

Why? What are you trying to do? Allocate one area per small structure?
Why not allocate one big area and allocate from that (like the tulip
drivers do for their TX and RX rings)?

I don't really know what you're trying to do/what the problem is because
there isn't enough context left in the original mail above, and I have
no idea whether the original mail appeared here or where I can read it.

> I should also check architectures other than x86 and ia64.

This is an absolute must.
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