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SubjectRe: 2.4.1-pre1 breaks XFree 4.0.2 and "w"
On Thu, Jan 11, 2001 at 06:08:21PM -0800, Linus Torvalds wrote:
>
> Could people with Athlons please verify that pre3 works for them?

It works fine.

> It also makes the fxsr disable act the same way the TSC disable does.

Note that there was a precise reason for not implementing it as the TSC disable
(infact at first in 2.2.x I was clearing the bigflag in x86_capabilities too).
The reason is that the way TSC gets disabled breaks /proc/cpuinfo. Furthmore
in english sense if "the cpu has fxsr or xmm" doesn't mean we can use them at
runtime in the kernel. Such wrong assumption was the source of the 2.4.0 md bug
in first place ;). So I'm not excited we're back in the old way. But of course
those are minor issues and I'm not that concerned /proc/cpuinfo changes even if
the CPU remains the same because nobody should need nofxsr and notsc anyways...

This is a leftover btw:

--- 2.4.1pre3/include/asm-i386/xor.h.~1~ Fri Jan 12 04:14:36 2001
+++ 2.4.1pre3/include/asm-i386/xor.h Fri Jan 12 04:23:32 2001
@@ -843,7 +843,7 @@
do { \
xor_speed(&xor_block_8regs); \
xor_speed(&xor_block_32regs); \
- if (HAVE_XMM) \
+ if (cpu_has_xmm) \
xor_speed(&xor_block_pIII_sse); \
if (md_cpu_has_mmx()) { \
xor_speed(&xor_block_pII_mmx); \
@@ -855,4 +855,4 @@
We may also be able to load into the L1 only depending on how the cpu
deals with a load to a line that is being prefetched. */
#define XOR_SELECT_TEMPLATE(FASTEST) \
- (HAVE_XMM ? &xor_block_pIII_sse : FASTEST)
+ (cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)


Andrea
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